The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of every substructure within any semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of a semiconductor device have resulted in very high-density circuit designs. Increasingly dense circuit design has not only improved a number of performance characteristics, it has also increased the importance of, and attention to, semiconductor material properties and behaviors.
The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Nearly every device must be smaller without degrading operational performance of the integrated circuitry. High packing density, low heat generation, and low power consumption, with good reliability must be maintained without any functional degradation. Increased packing density of integrated circuits is usually accompanied by smaller feature size.
As integrated circuits become denser, the dimensions of metal structures interconnecting transistors, channels between contacts, and other device features within an integrated circuit are significantly reduced—significantly altering the physical and electrical properties of those features. Consider, for example, reductions in the length of a CMOS transistor gate and, correspondingly, the length of a channel between source and drain structures of the transistor. Often, such reductions are prompted by requirements for increased drive current performance—especially for operation at reduced gate voltages.
The length of the gate structure is typically the smallest dimension in a planar transistor. Unfortunately, most conventional fabrication processes (e.g., lithography) are limited in their ability to reliably produce transistor features of extremely small dimension. In addition to fabrication process limitations, performance limitations are also a barrier to significant reductions in planar transistor gate lengths. Typically, reduced gate length can result in short channel effects that degrade transistor performance.
In CMOS devices having long channel lengths, gate voltage and a resulting field primarily control depletion of charge under the gate. In short channel devices, however, the channel region is also affected by source and drain voltages—causing an increased off-state current, due to VT roll-off, decreased sub-threshold slope, and degraded output current. In addition, since a lower gate voltage depletes a shortened channel, the barrier for electron injection from the source to the drain decreases—a phenomenon commonly referred to as drain induced barrier lowering (DIBL).
In response to these considerations and concerns, some have begun to design and produce multiple gate transistors—transistors that are non-planar. In theory, these designs provide more control over short channel structures by situating gate structure around two or more sides of the channel. Often these designs take the form of triple-gated transistors—transistors where gate structure is formed three dimensionally along three sides of a channel structure. In a number of conventional triple-gate processes, an SOI wafer is provided. The SOI wafer comprises a substrate, with an overlying oxide insulator, and a thin silicon layer above the oxide. Usually, a portion of the upper silicon layer is etched away leaving an isolated block of silicon that becomes the channel structure. A gate is then deposited or formed around the silicon block. The ends of the block are then doped to form source and drain regions.
Although such approaches are capable of producing multiple gate devices that offer improved performance over planar transistor designs, a number of production, performance and reliability issues still preclude their commercial viability in high-volume semiconductor fabrication. SOI wafers tend to be significantly more expensive than ordinary silicon substrates. Considerable overhead is added to fabrication processes by the etching processes involved in forming channel structures. Furthermore, channel surfaces exposed to the etch processes can incur damage that degrades their structural and electrical integrity throughout the lifetime of the device. Even if etch processes successfully form a channel structure, the physical form of the resulting channel structure may inherently cause a number of problems.
In most cases, etch and deposition processes used to form a triple-gate transistor will produce a channel block having squared, right-angle edges—particularly along the upper surface of the block (i.e., the surface farthest from substrate bulk). Subsequently, any gate structure formed over the block will also have squared, right-angled edges—particularly along the surface in direct contact with the channel block (i.e., the gate/channel interface). Sharp angles within semiconductor structures introduce structural discontinuities and instabilities (e.g., lattice structure instability) to those structures. Furthermore, such structures are inherently thicker at the edges than along the surfaces, resulting in differing performance characteristics or parameters (e.g., VT).
Some attempts have been made to round the upper edges of triple-gate channel blocks. Most such attempts rely on annealing or otherwise enhancing atomic rearrangement of the channel block, until surface tension begins to round the edges. Unfortunately, most such approaches have no way to selectively round only the upper edges of the channel block. As a result, rounding also occurs along the lower edges of the channel block (i.e., interface between the channel block and the substrate), and a channel structure resembling a quasi-cylindrical furrow is formed. This creates a number of performance problems, and complicates subsequent processing steps.
As a result, there is a need for a system that produces multiple-gated transistor structures in a commercially viable fabrication technology, one that provides selective engineering of certain structural features, such as channel edges, while optimizing device performance and reliability in an easy, efficient and cost-effective manner.